SIOREG  EQU 0xDE
SIODATA EQU 0xDF

CFBASE  EQU 0x98	    ;BASE ADDRESS OF PRIMARY IDE CONTROLLER
CFREG0	EQU	CFBASE+0	;DATA PORT
CFREG1	EQU	CFBASE+1	;READ: ERROR CODE, WRITE: FEATURE
CFREG2	EQU	CFBASE+2	;NUMBER OF SECTORS TO TRANSFER
CFREG3	EQU	CFBASE+3	;SECTOR ADDRESS LBA 0 [0:7]
CFREG4	EQU	CFBASE+4	;SECTOR ADDRESS LBA 1 [8:15]
CFREG5	EQU	CFBASE+5	;SECTOR ADDRESS LBA 2 [16:23]
CFREG6	EQU	CFBASE+6	;SECTOR ADDRESS LBA 3 [24:27 (LSB)]
CFREG7	EQU	CFBASE+7	;READ: STATUS, WRITE: COMMAND

CFLBA3	EQU	1
CFLBA2	EQU	1
CFLBA1	EQU	1
CFLBA0	EQU	1

ORG 0

JR CFINIT
JR CFSLBA
JR CFREAD

CFWAIT:                 ; wait cf read
    IN A, (CFREG7)
    AND $80
    JR NZ, CFWAIT
    RET

CFINIT:
    LD A, $04
    OUT (CFREG7), A     ;software reset
    JR CFWAIT
    LD A, $E0
    OUT (CFREG6), A     ;set LBA mode
    LD A, $01           ; 8 bit transfer
    OUT (CFREG1), A
    LD A, $EF
    OUT (CFREG7), A
    JR CFWAIT
    RET

CFSLBA:
    LD A, CFLBA0		;LBA 0
	OUT	(CFREG3), A
	LD A, CFLBA1		;LBA 1
	OUT	(CFREG4), A
	LD	A, CFLBA2		;LBA 2
	OUT	(CFREG5), A	
	LD	A, CFLBA3		;LBA 3
	AND	%00001111	    ;filter out LBA bits
	OR	%11100000	    ;mode LBA, master drive
	OUT	(CFREG6), A
	RET

CFREAD:
    JR CFWAIT
	IN A, (CFREG7)
	AND	%00001000	    ;filter out drq bit
	JR NZ, CFREAD
	IN A, (CFREG0)		;read data byte
	                    ;transfer data to RAM
    JR CFREAD
    RET